Ch. 5 Flip-Flops and related Devices: Fill in the blank Flashcards


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Digital System Design: Ronald J. Tocci
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1

The action of ________ a FF or latch is also called resetting.

Clearing

2

In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.

clock

3

If an input is activated by a signal transition, it is ________.

edge-trigerred

4

The ________ is the time interval immediately following the active transition of the clock signal.

hold time

5

The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.

flip-flop

6

The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs.

PRE, CLR, LOW

7

A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

13

8

An astable multivibrator is a circuit that ________.

produces a continuous output signal

9

Setup time specifies ________.

the minimum time for the control levels to be maintained on the inputs prior to the triggering edge of the clock in order for data to be reliably clocked into the FF

10

When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.

toggle

11

The advantage of a J-K flip-flop over an S-R FF is that ________.

it has no invalid states

12

The signal used to identify edge-triggered flip-flops is ________.

a triangle on the clock input

13

When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are:

S = 0, R = 1

14

The term hold always means ________.

no change

15

A gated S-R flip-flop is in the hold condition whenever ________.

the Gate Enable is HIGH and the S and R inputs are both LOW

16

A gated S-R flip-flop goes into the CLEAR condition when ________.

S is LOW; R is HIGH; EN is HIGH

17

An edge-triggered flip-flop can change states only when ________.

the trigger input changes levels

18

A positive edge-triggered flip-flop will accept inputs only when the clock ________.

changes from low to high

19

If data is brought into the J terminal and its complement to the K terminal, a J-K flip-flop operates as a(n) ________.

D Flip-flop

20

A flip-flop operation is described as a toggle when the result after a clock is ________.

Q and Q'change to opposite states

21

When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.

S = 0, R = 0

22
card image

The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.

point 4

23

The inputs on a 7474 D flip-flop are S, R, D, and CLK ________ is/are synchronous.

All of the above

24

The key to edge-triggered sequential circuits in VHDL is the _________.

process

25

The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a _________.

logic primitive

26

Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a __________.

simulator

27

In VHDL, each instance of a component is given a name followed by a _________ and the name of the library primitive.

colon

28

Most people would prefer to use ________ over HDL.

graphic desccriptions

29

In Altera’s Quartus II development software, basic logic gates are found in the ________ library.

primitives

30

In Altera’s Quartus II development software, a 74175 shift-register would be found in the ________ library.

maxplus2